library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity codeConverter1 is
   port( SW    :     IN    std_logic_vector  (  1  downto   0  );
         hex   :     OUT   std_logic_vector  (  6  downto   0  ) );
end codeConverter1;

architecture structural of codeConverter1 is
begin
   hex(6) <= not sw(1);
   hex(5) <= sw(0) or sw(1);
   hex(4) <= sw(0);
   hex(3) <= ( not sw(1) ) and sw(0);
   hex(2) <= ( not sw(0) ) and sw(1);
   hex(1) <= '0';
   hex(0) <= ( not sw(1) ) and sw(0);
end structural;


